A TSV technology refers to a packaging method for transmitting an electrical signal among a plurality of semiconductor chips by forming a via hole vertically penetrating the semiconductor chips when the semiconductor chips are laminated in a vertical direction. Due to the vertical integration, the entire system can be miniaturized, and due to the decrease in interconnection between chips, a high-integration, low-power, high-speed, and small-size packaging can be implemented.
Particularly, if a 3D System in Package (SiP) is implemented by applying the TSV technology to a SiP, an advantage of the SiP in terms of price can be maintained and the performance which is a relative disadvantage of the SiP compared with a System on Chip (SoC) can be improved.
There have been studies that attempt to utilize the TSV in integration of semiconductor sensor. In general, due to process characteristics, a semiconductor sensor chip is not processed as an ASIC driving circuit which is fabricated mainly through a CMOS process. Therefore, in most cases, a sensor chip and an ASIC chip are disposed horizontally in a sensor packaging and then connected to each other using a wirebond.
Such a horizontal integration method may cause an increase in size of the entire sensor system and requires a lot of processes and the wirebond itself is thin and long and thus cause an increase of a parasitic resistance/impedance, which has a great effect on the performance of a sensor. To solve this problem, a vertical integration method has been studied.
As such, technologies of integration in a vertical direction for size reduction and performance improvement are being actively developed, and particularly, the TSV technology has received the most attention. However, due to limitations of passivation and metal filling processes required for the TSV process, various problems such as a stress caused by heat occur.
Such problems restrict the utilization of a custom integrated circuit (custom IC) and decrease the degree of integration in a vertical process. Also, a sensor chip includes a wafer which is 5 to 10 times thicker than that of a system semiconductor or a memory chip in which the TSV is commonly used, and, thus, it is difficult to apply the general TSV technology to the sensor chip. Further, the sensor chip is very sensitive to contact resistance, and, thus, an operation of the sensor chip may be hampered by a parasitic resistance which is generated by a conventional thin and long TSV.
Accordingly, there is a need for a TSV technology specialized for sensor chips, a sensor packaging using the same, and a method for manufacturing the sensor packaging.